A configuration of a conventional MIM capacitor is disclosed in JP H7-326712A. FIG. 18 is a cross-sectional perspective view of a configuration of a conventional MIM capacitor 90.
The MIM capacitor 90 is provided with a substrate 20. The substrate 20 is made of an epitaxial layer or a substrate. Laminated in order on the substrate 20 are an insulating body 6, a metal area 2, an insulating body 4, and a metal area 1. In this way, the MIM capacitor 90 has a configuration in which the insulating body 4 is sandwiched by the metal area 1 and the metal area 2, and the capacitance value of the MIM capacitor 90 is determined by the opposing surface areas of the metal area 1 and the metal area 2.
FIG. 19 is a circuit diagram showing the configuration of an equivalent circuit of a conventional MIM capacitor 90. The equivalent circuit includes a capacitor 7 that has a capacitance value determined by the opposing surface areas of the metal areas 1 and 2. In this equivalent circuit, in which parasitic elements also are represented, a resistor 14 that represents the parasitic resistance of the metal area 1, which constitutes an upper portion electrode, and the metal area 2, and an inductor 18 that represents the parasitic inductance of the metal areas 1 and 2 are serially connected to one side of the capacitor 7.
A capacitor 8 represents the capacitance between the metal area 1, which constitutes an upper portion electrode, and the substrate 20. And a capacitor 10 represents the capacitance between the metal area 2, which forms a lower portion electrode, and the substrate 20. The capacitors 9 and 11 express the capacitance of the semiconductor in the substrate 20. The resistors 15 and 16 represent the resistance of the semiconductor in the substrate 20.
A MIM capacitor is disclosed in JP H5-283614A that is provided with a three layer structure and is similar to the configuration described above with reference to FIG. 18.
MIM capacitors such as this are generally often used when capacitance is necessary in a high frequency circuit. This is because the values of the parasitic elements occurring between the silicon substrate (epitaxial layer (hereafter “substrate”)) and the electrodes in a MIM capacitor configured in this way are relatively small compared to the capacitance of other configurations, and therefore there is little circuit deterioration.
Circuits that operate in the high frequency gigahertz (GHz) band are increasing recently in the communications field, thus bringing about a necessity for increasingly high performance in MIM capacitors. For example, with voltage controlled oscillators (hereafter, also “VCO”), the Q value of the MIM capacitor is one of the important elements determining the performance of the voltage controlled oscillator.
However, with the above-described conventional configuration of MIM capacitors, there is the problem that the Q value of the capacitance of the parasitic elements between the metal areas 1 and 2 and the substrate 20 is low, and therefore the Q value of the MIM capacitor as a whole, which includes the parasitic elements, also is low.
The Q value of a MIM capacitor is expressed, for example, by the formula 1 below, in which the capacitance value is C, the serial loss resistance inside the MIM capacitor is R, and the frequency at which the MIM capacitor is used is ω (=2×π×f: frequency).Q=1/(R×ω×C)  (Formula 1)
Deterioration in the Q value of the MIM capacitor here invites deterioration in the performance of the VCO. For this reason, there is a need for the Q value of MIM capacitors to be further increased. In order to further increase the Q value of MIM capacitors, it is necessary to improve the Q value of the parasitic capacitance between the metal areas and the substrate arranged in the MIM capacitor.
An object of the present invention is to provide a high-performance MIM capacitor.